View AX6108_1191632.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

AX6108 dot matrix liquid crystal graphic display column driver description AX6108 is a column (segment) driver for dot matrix liquid crystal graphic display systems. it stores the display data transferred from a 8-bit micro controller in the internal display ram and generates dot matrix liquid crystal driving signals. each bit data of display ram corresponds to the on/off state of a dot of a liquid crystal display to provide more flexible than character display. as it is internally equipped with 64 output drivers for display, it is available for liquid crystal graphic display with many dots. the AX6108, which is produced in the cmos process, can complete portable battery drive equipment in combination with a cmos microcontroller, utilizing the liquid crystal display's low power dissipation. moreover it can facilitate dot matrix liquid crystal graphic display system configuration in combination with the row (common) driver ax6107 features ? dot matrix liquid crystal graphic display column driver incorporating display ram ? ram data direct display by internal display ram ? ram bit data 1:on ? ram bit data 1:off ? internal display ram address counter preset, increment ? display ram capacity : 512 bytes (4096 bits) ? 8-bit parallel interface ? internal liquid crystal display driver circuit : 64 ? display duty cycle : drives liquid crystal panels with 1/32 - 1/64 duty cycle multiplexing ? wide range of instruction function : display data read/write, display on/off, set address, set display start line, read status ? lower power dissipation : during display 2 mw max ? power supply : vcc: 5v ? 10% ? liquid crystal display driving voltage : 8v to 17.0v ? cmos process ? 100-pin flat plastic package (fp-100) aslic microelectronics corp. ? ? 1q l a? |3 -- ? q page 1
------------------------------------------------------------------------------------------------------------------------ ax6018 dot matrix liquid crystal graphic display column driver ------------------------------------------------------------------------------------------------------------------------ absolute maximum ratings j -55 to + 125 tstg storage temperature j -20 to + 75 topr operating temperature 2, 5 v -0.3 to vcc + 0.3 v t2 terminla voltage (2) 4 v v ee - 0.3 to vcc + 0.3 v t1 terminal voltage (1) 3 v vcc -19.0 to vcc + 0.3 v ee 1 v ee 2 2 v -0.3 to +7.0 vcc supply voltage note unit value symbol item notes : 1. lsls may be destroyed if they are used beyond the absolute maximum ratings. in ordinary operation, it is desirable to use them within the recommended operation conditions. using them beyond these conditons may cause malfunction and poor reliability. 2. all voltage values are referenced to gnd = 0v. 3. apply the same supply voltage to v ee 1 and v ee 2 . 4. applies to v1l, v2l, v3l, v4l, v1r, v2r, v3r, and v4r. maintain vcc ? v1l=v1r ? v3l ? =v3r ? v4l=v4r ? v2l= v2r ? v ee 5. applies to m, frm, cl, rst, adc, p 1, p 2 , cs1, cs2, cs3, e, r/w, d/i, and db0 - db7. ------------------------------------------------------------------------------------------------------------------------ aslic microelectronics corp. ? ? 1q l a? |3 -- ? q page 2
ax6018 dot matrix liquid crystal graphic display column driver ------------------------------------------------------------------------------------------------------------------------ pin arrangement ------------------------------------------------------------------------------------------------------------------------ aslic microelectronics corp. ? ? 1q l a? |3 -- ? q page 3 y42 y41 y40 y39 y38 y37 y36 y35 y34 y33 y32 y31 y30 y29 y28 y27 y26 y25 y24 y23 50 49 48 47 46 45 44 43 42 31 32 33 34 35 36 41 40 39 38 37 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 y22 y21 y20 y19 y18 y17 y16 y15 y14 11 10 9 8 7 6 5 4 3 2 1 adc m vcc v4r v3r v2r v1r v ee 2 y64 y63 y62 y61 y60 y59 y58 y57 y56 y55 y54 y53 y52 y51 y50 y49 y48 y47 y46 y45 y44 y43 frm e p 1 p 2 cl d/i r/w rst cs1 cs2 cs3 nc nc nc db7 db6 db5 db4 db3 db2 db1 db0 gnd v4l v3l v2l v1l v 1 ee y1 y2 y3 y4 y5 y6 y7 y8 y9 y10 y11 y12 y13
ax6018 dot matrix liquid crystal graphic display column driver ------------------------------------------------------------------------------------------------------------------------ electrical characterisstics (gnd = 0 v, vcc = 4.5 to 5.5v, vcc - v ee = 8 to 17.0 v, ta = -20 to +75 j ) 7 during access access cycle = 1 mh z g a 500 -- -- i cc (2) 7 during display g a 100 -- -- i cc (1) dissipation current 8 vcc - vee= 15v ? i load = 0.1 ma k [ 7.5 -- -- r on driver on resistance 6 vin= vee - vcc g a 2 -- -2 i lsl liquid crystal supply leakage current 5 vin= gnd - vcc g a 5 -- -5 i tsl three-state (off) input current 4 vin= gnd - vcc g a 1 -- -1 i il input leakage current 3 i ol = -1.6ma v 0.4 -- -- v ol output low voltage 3 i oh = -205 g a v -- -- 2.4 v oh output high voltage 2 v 0.8 -- 0 v ilt 1 v 0.3xvcc -- 0 v ilc input low voltage 2 v vcc -- 2 v iht 1 v vcc -- 0.7xvcc v ihc input high voltage note test condition unit max typ min symbol item limit notes : 1. applies to m, frm, cl, rst, p 1 and p 2. 2. applies to cs1, cs2, cs3, e, r/w, d/i, and db0 - db7. 3. applies to db0 - db7. 4. applies to terminals except for db0 - db7. 5. applies to db0 - db7 at high impedance. 6. applies to v1l - v4l and v1r - v4r. 7. specified when liquid crystal display is in 1/64 duty cycle mode. operation frequency f clk = 250 khz ( p 1 and p 2 frequency) frame frequency f m = 70 hz (frm frequency) specified in the state of output terminal : not loaded input level : v ih = vcc (v) v il = gnd (v) measured at vcc terminal 8. resistance between terminal y and terminal v (one of v1l, v1r, v2l, v2r, v3l, v3r, v4l and v4r) when load current flows through one of the treminals y1 to y64. this value is specified under the following condition : ------------------------------------------------------------------------------------------------------------------------ ax6018 dot matrix liquid crystal graphic display column driver aslic microelectronics corp. ? ? 1q l a? |3 -- ? q page 4
------------------------------------------------------------------------------------------------------------------------ vcc - v ee = 15.5v v 1l = v 1r , v 3l = v 3r = vcc - 2/7 (vcc - v ee ) v 2l = v 2r , v 4l = v 4r = vcc + 2/8 (vcc - v ee ) the following is a description of the range of power supply voltage for liquid crystal display drive. apply positive voltage to v1l = v1r and v3l = v3r and negative voltage to v2l = v2r and v4l = v4r within the ? v range. this range allows stable impedance on driver output (ron). notice that ? v depends on power supply voltage vcc - v ee . correlation between driver correlation between power output waveform and power supply voltage vcc - v ee and ? v supply voltages for liquid crystal display drive ------------------------------------------------------------------------------------------------------------------------ ax6018 dot matrix liquid crystal graphic display column driver aslic microelectronics corp. ? ? 1q l a? |3 -- ? q page 5 ron terminal y (y1 - y64) v1l, v1r v3l, v3r v4l, v4r v2l, v2r ? ? ? ? v ? v vcc v1 (v1l =v1r) v3 (v3l = v3r) v4 (v4l = v4r) v2 (v2l = v2r) vee range of power supply voltage for liquid crystal display drive 8 17.0 5.0 3 ? v(v) vcc - v ee (v)
------------------------------------------------------------------------------------------------------------------------ terminal configuration ------------------------------------------------------------------------------------------------------------------------ ax6018 dot matrix liquid crystal graphic display column driver aslic microelectronics corp. ? ? 1q l a? |3 -- ? q page 6 input terminal ? ? ? ? vcc pmos nmos applicable terminals : m, frm, cl, rst, p 1, p 2, cs1, cs2, cs3, e, r/w, d/i, adc input/output terminal ? ? ? ? vcc pmos nmos ? ? ? ? vcc pmos nmos enable data (output circuit) (three state) applicable terminals : db0 - db7 (input circuit) ? ? output terminal pmos pmos nmos nmos v1l, v1r v3l, v3r v4l, v4r v2l, v2r vcc vcc v ee v ee applicable terminals : y1 - y64
------------------------------------------------------------------------------------------------------------------------ interface ac characteristics mpu interface (gnd = 0 v, vcc = 4.5 to 5.5 v, ta = -20 to +75 j 2 ns -- -- 20 t dhr data hold time (read) 1 ns -- -- 10 t dhw data hold time (write) 2, 3 ns 320 -- -- t ddr data delay time 1 ns -- -- 200 t dsw data setup time 1, 2 ns -- -- 10 t ah address hold time 1, 2 ns -- -- 140 t as address setup time 1, 2 ns 25 -- -- tf e fall time 1, 2 ns 25 -- -- tr e rise time 1, 2 ns -- -- 450 p wel e low level width 1, 2 ns -- -- 450 p weh e high level width 1, 2 ns -- -- 1,000 t cyc e cycle time note unit max typ min symbol item notes : 1. ------------------------------------------------------------------------------------------------------------------------ ax6018 dot matrix liquid crystal graphic display column driver aslic microelectronics corp. ? ? 1q l a? |3 -- ? q page 7 2.0v 0.8v p wel 2.0v 0.8v t t as as p wel cyc t t f t ah tr 2.0v 0.8v 2.0v 0.8v t t t ah dsw dhw e r/w cs1 - cs3 d/i db0 - db7 figure 1 cpu write timing
------------------------------------------------------------------------------------------------------------------------ notes : 2. 3. db0 - db7 : load circuit ------------------------------------------------------------------------------------------------------------------------ ax6018 dot matrix liquid crystal graphic display column driver aslic microelectronics corp. ? ? 1q l a? |3 -- ? q page 8 p wel 2.0v 0.8v t t as as p weh cyc t t f t ah tr 2.0v 0.8v 2.4v 0.4v t t t ah ddr dhr e r/w cs1 - cs3 d/i db0 - db7 figure 2 cpu read timing ? d1 c r rl d2 d3 d4 test point rl = 2.4k [ r = 11k [ c = 130pf (including jig capacitance) diodes d1 - d4 are all 1s2074 h
------------------------------------------------------------------------------------------------------------------------ clock timing (gnd = 0 v, vcc = 4.5 to 5.5 v, ta = -20 to + 75 j ) fig. 3 ns 150 -- -- tf p 1 - p 2 fall time fig. 3 ns 150 -- -- tr p 1 - p 2 rise time fig. 3 ns -- -- 625 t d21 p 2 - p 1 phase difference fig. 3 ns -- -- 625 t d12 p 1 - p 2 phase difference fig. 3 ns -- -- 1,875 t wh p 2 p 2 high level width fig. 3 ns -- -- 1,875 t wh p 1 p 1 high level width fig. 3 ns -- -- 625 t wl p 2 p 2 low level width fig. 3 ns -- -- 625 t wl p 1 p 1 low level width fig. 3 ns 20 -- 2.5 t cyc p 1, p 2 cycle time test condition unit max typ min symbol item limit figure 3 external clock waveform aslic microelectronics corp. ? ? 1q l a? |3 -- ? q page 9 tcyc t wh p 1 tf tr 0.7 vcc 0.3 vcc t wl p 1 t d12 t d21 0.7 vcc 0.3 vcc tf t tr tcyc t wl p 2 wh p 2 p 1 p 2
------------------------------------------------------------------------------------------------------------------------ ax6018 dot matrix liquid crystal graphic display column driver ------------------------------------------------------------------------------------------------------------------------ display control timing (gnd = 0v, vcc = 4.5 to 5.5 v, ta = -20 to +75 j ) fig. 4 g s -- -- 35 t whcl cl high level width fig. 4 g s -- -- 35 t wlcl cl low level width fig. 4 g s 2 -- -2 t dm m delay time fig. 4 g s 2 -- -2 t dfrm frm delay time test condition unit max typ min symbol item limit figure 4 display control signal waveform aslic microelectronics corp. ? ? 1q l a? |3 -- ? q page 10 0.7vcc 0.3vcc 0.7vcc 0.3vcc t t t t t 0.7vcc 0.3vcc cl frm m wlcl dfrm whcl dfrm dm
------------------------------------------------------------------------------------------------------------------------ ax6018 dot matrix liquid crystal graphic display column driver ------------------------------------------------------------------------------------------------------------------------ block diagram aslic microelectronics corp. ? ? 1q l a? |3 -- ? q page 11 v1l v2l v3l v4l y1 y2 y3 y62 y63 y64 v1r v2r v3r v4r liquid crystal display driver circuit 1 2 3 62 63 64 64 64 1 2 3 display date latch 62 63 64 ? xy address counter display data ram 4096 bit instruction register z address counter display start line register display on/off input register output register busy flag i/o buffer interface control cs1, cs2, cs3 9 9 6 6 6 m adc vcc gnd v v ee1 ee2 ? rst p 1 p 2 r/w d/i e db0 - db7 3 8 8 8 cl frm ? ? ? ?
------------------------------------------------------------------------------------------------------------------------ ax6018 dot matrix liquid crystal graphic display column driver ------------------------------------------------------------------------------------------------------------------------ terminal functions data/instruction. d/i = high : indicates that the data of db0 to db7 is display data. d/i = low : indicates that the data of db0 to db7 is display control data. mpu i 1 d/i read/write. r/w = high : data appears at db0 to db7 and can be read by the cpu. when e = high, cs1, cs2 = low and cs3 = high. r/w = low : db0 to db7 can accept at fall of e when cs1, cs2 = low and cs3 = high. mpu i 1 r/w enable. at write (r/w = low) : data of db0 to db7 is latched at the fall of e. at read (r/w = high) : data appears at db0 to db7 while e is at high level. mpu i 1 e chip selection. data can be input or output when the terminals are in the following conditions : terminal name cs1 cs2 cs3 condition l l h mpu i 3 cs1 cs2 cs3 power supply for liquid crystal display drive. apply the voltage specified depending on liquid crystals within the limit of vee through vcc. v1l (v1r), v2l (v2r) : selection level v3l (v3r), v4l (v4r) : non-selection level power supplies connected with v1l and v1r (v2l & v2r, v3l & v3r, v4l & v4r) should have the same voltages. power supply 8 v1l, v1r v2l, v2r v3l, v3r v4l, v4r power supply for liquid crystal display drive circuit. recommended power supply voltage is vcc - vee = 8 to 17.0 v. connect the same power supply to v ee 1 and v ee 2 . v ee 1 and v ee2 are not connected each other in the lsi. power supply 2 v ee 1 v ee 2 power supply for internal logic. recommended voltage is : gnd = 0 v vcc = 5 v ? 10% power supply 2 vcc gnd functions connected to i/o number of terminals terminal name aslic microelectronics corp. ? ? 1q l a? |3 -- ? q page 12
------------------------------------------------------------------------------------------------------------------------ ax6018 dot matrix liquid crystal graphic display column driver ------------------------------------------------------------------------------------------------------------------------ unused terminals. don't connect any lines to these terminals. open 3 nc the following registers can be initialized by setting the rst signal to low level. 1. on/off register 0 set (display off) 2. display start line register line 0 set (displays from line 0) after releasing reset, this condition can be changed only by instruction. cpu or external cr i 1 rst liquid crystal display column (segmnet) drive output. these pins outputs light on level when 1 is in the display ram, and light off level when 0 is it. relation among output level, m, and display data (d) is as follows: m d output level 1 0 1 0 1 0 v1 v3 v2 v4 liquid crystal display o 64 y1 - y64 2-phase clock signal for internal operation. the p 1 and p 2 clocks are used to preform operations (i/o of display data and execution of instructions) other than display. ax6107 i 2 p 1, p 2 synchronous signal to latch display data. the rising cl signal increments the disiplay output address counter and latches the display data. ax6107 i 1 cl display synchronous signal (frame signal). presets the 6-bit display line counter and synchronizes the common signal with the frame timing when the frm signal becomes high. ax6107 i 1 frm switch signal to convert liquid crystal drive wavefojrm into ac. ax6107 i 1 m data bus, three-state i/o common terminal. mpu i/o 8 db1 - db7 address control signal to determine the relation between y address of display ram and terminals from which the data is output. adc = high : y1 : $0, y64 : $63 adc = low : y64 : $0, y1 : $63 vcc/gnd i 1 adc functions connected to i/o number of terminals terminal name note : 1 corresponds to high level in positive logic. aslic microelectronics corp. ? ? 1q l a? |3 -- ? q page 13
AX6108 dot matrix liquid crystal graphic display column driver ------------------------------------------------------------------------------------------------------------------------ function of each block interface control 1. i/o buffer data is transferred through 8 data bus lines (db0 - db7) . db7 : msb (most significant bit) db0 : lsb (lleast significant bit) data can neither be input nor output unless cs1 to cs3 are in the active mode. therefore, when cs1 to cs3 are not in active mode it is useless to switch the signals of input terminals except rst and adc: that is namely, the internal state is maintained and no instruction excutes. besides, pay attention to rst and adc which operate irrespectively of cs1 to cs3. 2. register both input register and output register are provided to interface to an mpu whose speed is different from that of internal operation. the selection of these registers depend on the combination of r/w and d/i signals (table 1). a. input register the input register is used to store data temporarily before writing it into display data ram. the data from mpu is written into the input register, then into display data ram automatically by internal operation. when cs1 to cs3 are in the active mode and d/i and r/w select the input register as shown in table 1, data is latched at the fall of the e signal. b. output register the output register is used to store data temporarily that is read from display data ram. to read out the data from output register, cs1 to cs3 should be in the active mode and both d/i and r/w should be 1. with the read display data instruction, data stored in the output register is output while e is high level. then, at the fall of e, the display data at the indicated address is latched into the output register and the address is increased by 1. the contents in the output register are rewritten by the read display data instructiion. but ree held by address set instruction, etc. therefore, the data of the specified address cannot be output with the read display data instruction right after the address is set, but can be output at the second read of data. that is to say, one dummy read is necessary. figure 5 shows the cpu read timing. _________________________________________________________________________________ table 1 register selection instruction 0 0 busy check. read of status data. 1 0 writes data into input register as internal operation (input register ? display data ram) 0 1 reads data out of output register as internal operation (display data ram ? output register) 1 1 operation r/w d/i ------------------------------------------------------------------------------------------------------------------------ ??1qla?|3--?q aslic microelectronics corp. page 14 sales by titron international corp.
AX6108 dot matrix liquid crystal graphic display column driver ------------------------------------------------------------------------------------------------------------------------ figure 5 cpu read timing ------------------------------------------------------------------------------------------------------------------------ AX6108 dot matrix liquid crystal graphic display column driver ??1qla?|3--?q aslic microelectronics corp. page 15 sales by titron international corp. d/i r/w e n + 2 n + 1 n data at address n data at address n + 1 data read address n + 1 busy check read data at address n busy check read data (dummy) busy check write address n busy check address output register db0 - db7
------------------------------------------------------------------------------------------------------------------------ busy flay busy flag = 1 indicates that AX6108 is operating and no instructions except status read instruction can be accepted. the value of the busy flag is read out on db7 by the status read instruction. make sure that the busy flag is reset (0) before issuing insstructions. figure 6 busy flag display on/off flip/flop the display on/off flip/flop selects one of two states, on state and off state of segments y1 to y64. in on state, the display data corresponding to that in ram is output to the segments. on the other hand, the display data at all segments. on the other hand, thedisplay data at all segments disappear in off state independent of the data in ram. it is controlled by display on/off instruction. rst signal = 0 sets the segments in off state. the status of the flip/flop is output to db5 by status read instruction. display on/off instruction does not influence data in ram. to control display data latch by this flip/flop, cl signal (display synchronous signal) should be input correctly. display start line register the display start line register specifies the line in ram which corresponds to the top line of lcd panel, when displaying contents in display data ram on the lcd panel. it is used for scrolling of the screen. 6-bit display start line information is written into this register by the display start line set instruction. when high level of the frm signal starts the display, the information in this register is transferred to the z address counter, which controls the display address, presetting the z address counter. x, y adddress counter a 9-bit counter which designates addresses of the internal display data ram. x address counter (upper 3 bits) and y address counter (lower 6 bits) should be set to each address by the respective instructions. ------------------------------------------------------------------------------------------------------------------------ AX6108 dot matrix liquid crystal graphic display column driver ??1qla?|3--?q aslic microelectronics corp. page 16 sales by titron international corp. e busy flag t busy 1/f clk clk clk ?? t busy ?? 3/f f is p 1, p 2 frequency
------------------------------------------------------------------------------------------------------------------------ 1. x address counter ordinary register with no count functions. an address is set by instruction. 2. y address counter an address is set by instruction and is increased by 1 automatically by r/w operations of display data the y address counter loops the values of 0 to 63 to count. display data ram stores dot data for display. 1-bit data of this ram corresponds to light on (data = 1) and light off (data = 0) of 1 dot in the display panel. the correspondence between y addresses of ram and segment pins can be reversed by adc signal. as the adc signal controls the y address counter, reversing of the signal during the operation causes malfunction and destruction of the contents of register and data of ram. therefore, never fail to connnect adc pin to vcc or gnd when using. figure 7 shows the relations between y address of ram and segment pins in the cases of adc = 1 and adc = 0 (display start line = 0, 1/64 duty cycle). ------------------------------------------------------------------------------------------------------------------------ AX6108 dot matrix liquid crystal graphic display column driver ------------------------------------------------------------------------------------------------------------------------ ??1qla?|3--?q aslic microelectronics corp. page 17 sales by titron international corp.
------------------------------------------------------------------------------------------------------------------------ AX6108 dot matrix liquid crystal graphic display column driver ------------------------------------------------------------------------------------------------------------------------ ??1qla?|3--?q aslic microelectronics corp. page 18 sales by titron international corp. com1 (ax61203 x1) com2 (ax61203 x2) com3 (ax61203 x3) com4 (ax61203 x4) com5 (ax61203 x5) com6 (ax61203 x6) com7 (ax61203 x7) com8 (ax61203 x8) com9 (ax61203 x9) com62 (ax61203 x62) com63 (ax61203 x63) com64 (ax61203 x64) lcd display pattern 0 1 1 1 1 1 1 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 0 0 0 1 0 1 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 y1 y2 y3 y4 y5 y 62 y 63 y64 1 0 1 2 3 4 5 61 62 63 ram y address db0(lsb) db1 db2 db3 db4 db5 db6 db7(msb) ? ? ? ? ? ? ? ? line 0 line 1 line 2 x = 0 display ram data x = 1 x = 7 line 62 line 63 adc = 1 (connected to vcc) ax61202 pin name
------------------------------------------------------------------------------------------------------------------------ AX6108 dot matrix liquid crystal graphic display column driver ------------------------------------------------------------------------------------------------------------------------ ??1qla?|3--?q aslic microelectronics corp. page 19 sales by titron international corp. com1 (ax61203 x1) com2 (ax61203 x2) com3 (ax61203 x3) com4 (ax61203 x4) com5 (ax61203 x5) com6 (ax61203 x6) com7 (ax61203 x7) com8 (ax61203 x8) com9 (ax61203 x9) com62 (ax61203 x62) com63 (ax61203 x63) com64 (ax61203 x64) lcd display pattern 0 1 1 1 1 1 1 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 1 0 0 0 1 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 1 1 1 1 1 1 0 0 0 1 0 1 1 0 0 0 0 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 y1 y2 y3 62 63 1 0 1 2 3 4 5 61 62 63 ram y address db0(lsb) db1 db2 db3 db4 db5 db6 db7(msb) ? ? ? ? ? ? ? ? line 0 line 1 line 2 x = 0 display ram data x = 1 x = 7 line 62 line 63 adc = 0 (connected to gnd) y 64 y y y 61 y 59 ax61202 pin name
z address counter the z address counter generates addresses for outputting the display data synchronized with the common signal. this counter consists of 6 bits and counts up at the fall of the cl signal. at the high level of frm, the contents of the display start line register is preset at the z counter. display data latch the display data latch stores the display data temporarily that is output from display data ram to the liquid crystal driving circuit. data is latched at the rise of the cl signal. the display on/off instruction controls the data in this latch and does not influence data in display data ram. liquid crystal display driver circuit the combination of latched display data and m signal causes one of the 4 liquid crystal driver levels, v1, v2, v3 and v4 to be output. reset the system can be initialized by setting rst terminal at low level when turning power on. 1. display off 2. set display start line register line 0. while rst is low level, no instruction except status read can be accepted. therefore, execute other instructions after making sure that db4 = 0 (clear reset) and db7 = 0 (ready) by status read instruction. the conditions of power supply at initial power up are shown in table 1. do not fail to set the system again becaise reset during operation may destroy the data in all the registers except on/off register and in ram. ------------------------------------------------------------------------------------------------------------------------ AX6108 dot matrix liquid crystal graphic display column driver ------------------------------------------------------------------------------------------------------------------------ ??1qla?|3--?q aslic microelectronics corp. page 20 sales by titron international corp. table 1 power supply initial conditions item symbol min typ max unit reset time rise time t rst tr 1.0 200 g s ns 4.5v t tr rst 0.7vcc 0.3vcc rst
display control instructions outline table 2 shows the instructions. read/write (r/w) signal, data/instruction (d/i) signal, and data bus signals (db0 to db7) are also called instructions because the internal operation depends on the signals from the mpu. these explanations are detailed in the following pages. generally, there are following three kinds of instructions : 1. instruction to set addresses in the internal ram. 2. instruction to transfer data from/to the internal ram. 3. other instructions. in general use, the second type of instruction is used most frequently. since y address of the internal ram is increased by 1 automatically after writing (reading) data, the program can be shortened. during the execution of an instruction, the system cannot accept instructions other than status read instruction. send instructions from mpu after making sure that the busy flag is 0, which is proof that an instruction is not being excuted. ------------------------------------------------------------------------------------------------------------------------ AX6108 dot matrix liquid crystal graphic display column driver ------------------------------------------------------------------------------------------------------------------------ ??1qla?|3--?q aslic microelectronics corp. page 21 sales by titron international corp.
table 2 instructions ?? 1qla?|3--?q aslic microelectronicss corp. page22 code instructions display on/off display start line set page (x address) set address status read write display data read display data r/w 0 0 0 0 1 0 1 d/i 0 0 0 0 1 1 0 db7 0 1 1 0 busy write data read data db6 0 1 0 1 0 db5 1 display start line (0 - 63) 1 y address (0 - 63) on/ off db4 1 1 reset db3 1 1 0 db2 1 page (0 - 7) 0 db1 1 0 db0 1/0 0 functions controls display on/off. ram data and inte rnal status are not affected. 1: on, 0:off. specifies the ram line displayed at the top of the screen. sets the page (x address) of ram at the page (x address) register. sets the y address in the y address counter. reads the status. reset 1 : reset 0 : normal on/off 1 : display off 0 : display on busy 1 : internal operation 0 : ready writes data db0 (lsb) to db7 (msb) on the da ta bus into display ram. has access to the address of the display ram specified in advance. after the access, y address is is increased by 1. reads data db0 (lsb) to db7 (msb) from the display ram to the data bus. note : 1. busy time varies with the frequency (f ) of p 1, and p 2. (1/f ?? t ?? 3/f ) clk clk busy clk

!
"
#

$ %&

"'() #
*+,
'() "&'+-'-)#

./

************************************************************************************************************************ 0(%
&.1/
2

/ 3 ************************************************************************************************************************

4
-+

************************************************************************************************************************ 0(%
&.1/
2

/ 3 ************************************************************************************************************************

4
-)

0
"
#

0

45&
&
6 7 8
"
#

8

8

3

45

************************************************************************************************************************ 0(%
&.1/
2

/ 3 ************************************************************************************************************************

4
-9

status read busy : when busy is 1, the lsi is executing internal operations. no instructions are accepted while busy is 1, so you should make sure that busy is 0 before writing the next instruction. on/off : shows the liquid crystal display conditions: on condition or off condition. when on/off is 1, the display is in off condition. when on/off is 0, the display is in on condition. reset : reset = 1 shows that the system is being initialized. in this condition, no instructions except status read can be accepted. reset = 0 shows that initializing has finished and the system is in the usual operation condition. write display data writes 8-bit data dddddddd (binary) into the display data ram. then y address is increased by 1 automatically. read display data reads out 8-bit data dddddddd (binary) from the display data ram. then y address is increased by 1 automatically. one dummy read is necessary right after the address setting. for details, refer to the explanation of output register in "function of each block". ??1qla?|3--?q aslic microelectronics corp. page 26 sales by titron international corp. 0 0 0 1 1 1 r/w d/i db7 db0 code high-order bit low-order bit 1 a a a 0 r/w d/i db7 db0 code high-order bit low-order bit 1 d d d d d d d d 0 r/w d/i db7 db0 code high-order bit low-order bit 1 d d d d d d d d 0 r/w d/i db7 db0 code high-order bit low-order bit 1 d d d d d d d d
------------------------------------------------------------------------------------------------------------------------ AX6108 dot matrix liquid crystal graphic display column driver ------------------------------------------------------------------------------------------------------------------------ use of AX6108 interface with ax6103 (1/64 duty cycle) ??1qla?|3--?q aslic microelectronics corp. page 27 sales by titron international corp. ? vcc v1l, v1r v6l, v6r v5l, v5r v2l, v2r v gnd ee x1 x64 vcc v1 v6 v5 v2 v ee ? ? ? ? ? ? ? vcc vcc v1 v2 v3 v4 v ee rf cf r cr c com1 com64 lcd panel 64x64 dots seg1 seg64 open open shl ds1 ds2 th cl1 fs m/s fcs stb dl dr m cl2 frm p 1 p 2 y1 y64 m cl frm p 1 p 2 vcc v1l, v1r v2l, v2r v3l, v3r v4l, v4r v ee1, ee2 v gnd ax61202 cs1 cs2 cs3 r/w d/i e db0 db1 db2 db3 db4 db5 db6 db7 cpu - - + + - + - + ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? contrast r3 v1 r3 v6 r3 v3 r3 v4 r1 r1 r2 r1 r1 r3 v5 r3 v2 v ee -10v r3 = 15 [ adc rst vcc external cr power supply circuit ~ ax61203 +5v (vcc)
-------------------------------------------------------------------- ---------------------------------------------------- ax6102 dot matrix liquid crystal graphic display column driver -------------------------------------------------------------------- ---------------------------------------------------- figure 10 lcd driver timing chart (1/64 duty cycle)

page28

!" #
$

% !
~ ~ y1 y64

AX6108 dot matrix liquid crystal graphic display column driver ------------------------------------------------------------------------------------------------------------------------ interface with cpu 1. example of connection with hd6800 figure 11 example of connection with hd6800 series in this decoder, addresses of AX6108 in the address area of hd6800 are : read/write of the display data $ffff write of display insstruction $ffff read out of status $ffff therefore, you can control AX6108 by reading/writing the data at these addresses. ------------------------------------------------------------------------------------------------------------------------ AX6108 dot matrix liquid crystal graphic display column driver ??1qla?|3--?q aslic microelectronics corp. page29 decoder a15 a1 vma a0 r/w p 2 d0 d7 res ~ ~ hd6800 cs1 cs2 cs3 d/i r/w e db0 db7 rst ~ vcc ? ? vcc decoder a15 a1 vma a0 r/w p 2 d0 d7 res ~ ~ hd6800 cs1 cs2 cs3 d/i r/w e db0 db7 rst ~ vcc ? ? vcc AX6108
------------------------------------------------------------------------------------------------------------------------ 2. example of connection with hd6801 ? set hd6801 to mode 5. p10 to p14 are used as the output port and p30 to p37 as the data bus. ? 74ls154 4-to-16 decoder generates chip select signal to make specified AX6108 active after decoding 4 bits of p10 to p13. ? therefore, after enabling the operation by p10 to p13 and specifying d/i signal by p14, read/write from/to the external memory area ($0100 to $01fe) to control AX6108. in this case, ios signal is output from sc1 and r/w signal from sc2. ? for details of hd6800 and hd6801, refer to their manuals. ------------------------------------------------------------------------------------------------------------------------ AX6108 dot matrix liquid crystal graphic display column driver ??1qla?|3--?q aslic microelectronics corp. page30 hd6801 cs1 cs2 cs3 d/i r/w e db0 db7 AX6108 vcc no.1 74ls154 a b c d y0 y1 g1 g2 y15 p10 p11 p12 p13 (ios)(sc1) (r/w)(sc2) p14 e p30 p31 p37 (date bus) db1
------------------------------------------------------------------------------------------------------------------------ example of application note : in this example, two ax6107s output the equivalent waveforms. so, stand-alone operation is possible. in this case, connect com1 and com65 to x1, com2 and com66 to x2, ..., and com64 and com128 to x64. however, for the large screen display, it is better to drive in 2 rows as in this example to guarantee display qualitty. ??1qla?|3--?q aslic microelectronics corp. page31 AX6108 no. 9 y1 y64 ~ AX6108 no. 10 y1 y64 ~ AX6108 no. 16 y1 y32 ~ y1 y64 AX6108 no. 1 y1 y64 AX6108 no. 2 y1 y64 AX6108 no. 8 ~ ~ ~ com1 com2 com3 com64 lcd panel 128 x 480 dots com65 com66 com67 com128 ax6107 (slave) ax6107 (master) x1 x2 x3 x1 x2 x3 x64 x64 ~ ~ ??

▲Up To Search▲

Price & Availability of AX6108

	To Download AX6108 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .